1. Technical Field
The present invention relates in general to data processing and in particular to performance monitoring within a data processing system. Still more particularly, the present invention relates to performance monitoring within a multithreaded processor.
2. Description of the Related Art
In order to extract optimum performance from a processor, hardware and software engineers detect and analyze the processor's dynamic behavior. In the past, most of the processor states useful in such processor analysis were accessible to external instrumentation. For example, at low levels of integration, most machines states, bus transactions, and other useful signals were detectable on module interconnects, edge connectors, and chip backplanes. Thus, data could be easily captured and post-processed for use in processor performance analysis.
However, as the level of integration has increased, thereby rendering processor states inaccessible to external instrumentation, it has become necessary to integrate performance monitoring circuitry within the processor in order to capture the empirical data required to optimize both hardware and software. Such on-board performance monitors typically include one or more counters that each count occurrences of a selected event indicative of processor performance, such as processor cycles, instructions executed, or cache misses. While currently available performance monitors may provide adequate data to analyze the dynamic behavior of conventional processors, a conventional performance monitor that utilizes a single counter to record all occurrences of a selected event cannot provide sufficiently detailed performance data for a multithreaded processor that provides hardware support for multiple concurrent threads. For example, a conventional performance monitor cannot provide information indicating the number of cache misses attributable to each thread, the number of processor cycles utilized by each thread, or how often and why thread switches are occurring.
Consequently, it would be desirable to provide an improved performance monitor for a multithreaded processor that is capable of independently monitoring events generated by each of a plurality of threads and, in particular, is capable of monitoring thread switch events.